Course Objectives

Getting hands-on experience in basic to complex digital chip design flow starting from RTL netlist to GDSII. The flow also includes analyzing reports/constraints and tweaking the same to meet Power, performance and Area goals at various stages.

Course Syllabus

VLSI Physical Design involves thorough understanding of basic digital design, CMOS fundamentals, Partitioning, Floorplanning, Place & route, Static Timing Analysis (STA ), timing closure, Signal Integrity analysis, parasitic (RC) extraction, Power analysis, Physical verification, Electrical verification, DFM/DFY and Tapeout related topics.

The course starts with pre-requisite courses in Unix OS, Programming & Shell/Perl / TCL scripting languages. To appreciate the concepts better student should be prepared to attempt all assignments, Labs. This will ensure the students pass with flying colours.

 

1. Introduction to VLSI Design

2. Basic Electronics and CMOS fundamentals

3. Basic Digitals ( Combinational & Sequential ) Design concepts

4. Inverter, STD Cell Design concepts

5. Hardware Description Language Techniques

6. Introduction to Static Timing Analysis

7. Mini Project

8. Synthesis  – SDC ( Synopsys Design Constraints )

9. Timing Constraints & STA (Detailed)

10. Design Partitioning

11. Design Floor Planning and Power Planning

12. Design Placement

13. Clock Tree Synthesis

14. Design Routing

15. Parasitic Extraction and Timing Analysis

16. Signal Integrity

17. IR Drop Analysis

18. OCV Analysis

19. Low Power Design Techniques

20. Physical Verification

21. Electrical Verification

22. SignOff

23. Major Project

Prerequisites

All fresh and experienced professionals with electronics degree B.Tech / M.Tech or MSc electronics having 60% or above.

 Course Format

 The class will consist of classroom lecture, of duration 2.5 hrs daily and  6 hrs of the lab. Lab access is unlimited