Getting hands-on experience in basic to complex digital chip design flow starting from RTL netlist to GDSII. The flow also includes analyzing reports/constraints and tweaking the same to meet Power, performance and Area goals at various stages.
VLSI Physical Design involves thorough understanding of basic digital design, CMOS fundamentals, Partitioning, Floorplanning, Place & route, Static Timing Analysis (STA ), timing closure, Signal Integrity analysis, parasitic (RC) extraction, Power analysis, Physical verification, Electrical verification, DFM/DFY and Tapeout related topics.
The course starts with pre-requisite courses in Unix OS, Programming & Shell/Perl / TCL scripting languages. To appreciate the concepts better student should be prepared to attempt all assignments, Labs. This will ensure the students pass with flying colours.
All fresh and experienced professionals with electronics degree B.Tech / M.Tech or MSc electronics having 60% or above.
The class will consist of classroom lecture, of duration 2.5 hrs daily and 6 hrs of the lab. Lab access is unlimited